The present invention relates generally to a semiconductor device and method for manufacturing the same and more particularly to a semiconductor device that may include a high breakdown-voltage transistor and a method for manufacturing the same.
A semiconductor device, such as a non-volatile semiconductor memory device using non-volatile memory cells, can require high voltages to program or erase data in a memory cell. Thus, transistors that can withstand a high voltage are needed.
One such example of a conventional high breakdown-voltage transistor is disclosed in Japan Patent Publication No. 2000-299390 and illustrated in FIG. 8.
Referring now to FIG. 8, a cross-sectional diagram of a conventional high breakdown-voltage transistor is set forth and given the general reference character 800.
Conventional high breakdown-voltage transistor 800 is a MOSFET (metal oxide semiconductor field effect transistor). Conventional high breakdown-voltage transistor 800 is formed in an element region defined by an element isolation region 54 on a silicon substrate 48. A gate electrode 52 is formed on the element region. A side-wall film 50 covers side surfaces of the gate 52. A well is formed in the semiconductor substrate 48. Incidentally, the boundary between the well and the semiconductor substrate 48 is not shown in FIG. 8. Low concentration source/drain regions 58 and high concentration source/drain regions 56 are formed in the well. An intra-substrate high-concentration contour line 60 indicates a peak of the impurity concentration of the well in the vicinity of the high concentration source/drain regions 56.
Conventional high breakdown-voltage transistor 800 can suffer from a decreased breakdown voltage as will now be explained.
First, there can be a large difference in silicon oxide film thickness of element isolation region 54 between ion implantation steps forming the well and the source/drain regions. Also, in a semiconductor device including complementary MOSFETs (CMOS) and non-volatile memory transistors (such as floating gate transistors), the thickness of a gate oxide film can vary greatly between the non-volatile memory transistors, a high break-down voltage transistor for controlling the non-volatile memory transistor, and CMOS transistors used for logic. To manufacture such a semiconductor device, gate oxidation and etching may be repeated many times. When a gate oxide film is etched, the silicon oxide film in an element isolation region (for example, element isolation region 54) is typically etched simultaneously. However, ions are typically implanted to form a well before gate oxidation and ions are typically implanted to from source/drain regions after the gate oxidation process are completed. This results in a large difference in thickness of the silicon oxide film in the element isolation region 54 between when the well-forming ions are implanted and when the source/drain forming ions are implanted.
The above-mentioned difference in thickness of the silicon oxide film can be particularly problematic when the element isolation region 54 has a moderate slope near an element region end 62. When an element isolation region 54 is formed by thermal oxidation at about 1100xc2x0 C., the inclination of an element isolation region 54 may have such a moderate slope near the element region end 62. Also, a trench may be formed under conditions that cause a moderate slope and may then be filled with a silicon oxide film to form element isolation region 54 having a moderate slope near the element region end 62.
The reason why a sufficiently high breakdown voltage may not be obtained if the above-mentioned conditions occur will now be described with reference to FIG. 9.
Referring now to FIG. 9, a cross section of conventional high-voltage transistor 800 in the vicinity of element region end 62 is set forth.
An upper surface of element isolation region 54 at the time of well-forming ion implantation is indicated by a broken line. At the time of source/drain forming ion implantation, the upper surface of element isolation region 54 is indicated by the solid line. The intra-substrate high-concentration contour line 60 produced in the substrate as a result of the well-forming ion implantation is indicated by a dot dashed line. The high concentration source/drain region 56 is indicated by another dashed line.
It is noted that due to the thick beveled shape of the element isolation region 54 at the time of well-forming ion implantation, the well tapers near the element region end 62 so that it is much more shallow. However, because the element isolation region 54 has a much thinner beveled shape at the time of the source/drain forming ion implantation, the high concentration source/drain region 56 does not taper as much, relative to the well. Due to this, a distance L1 between the high concentration source/drain region 56 and the intra-substrate high-concentration contour line 60 in a central area is greater than a distance L2 between the high concentration source/drain region 56 and the intra-substrate high-concentration contour line 60 near the element isolation region 54. This results in a decrease in a breakdown voltage of conventional high-voltage transistor 800.
Another conventional high-voltage transistor is disclosed in Japan Patent Application laid-Open No. Hei 8-181223 and illustrated in FIG. 10.
In FIG. 10(a), a cross-sectional diagram of a conventional high breakdown-voltage transistor is set forth and given the general reference character 1000. In FIG. 10(b), a plan view of conventional high-voltage breakdown transistor 1000 is set forth.
Referring now to FIG. 10(a), conventional high-voltage breakdown transistor 1000 is a MOSFET. Conventional high breakdown-voltage transistor 1000 is formed in an element region defined by an element isolation region 114 on a silicon substrate 108. The transistor 1000 includes a low concentration source/drain region 118 and a high concentration source drain region 116, which are formed in a well, and a gate electrode 112. An intra-substrate high-concentration contour line 120 indicates a peak of the impurity concentration of the well in the vicinity of the high concentration source/drain regions 116.
In conventional high-voltage breakdown transistor 1000, gate 112 is also disposed over the element region end 122. This can prevent the high concentration source/drain region 116 from being formed at the element region end 122, so that the distance between the high concentration source/drain region 116 and the intra-substrate high concentration contour line 120 may not be reduced near the element region end 122.
Referring now to FIG. 10(b), the layout of the gate 112 is illustrated. Gate 112 is disposed over the element region end 122 (FIG. 10(a)). Thus, gate 112 is formed in a loop pattern. This can cause increased chip size as will be discussed below.
Referring now to FIG. 11, a schematic diagram of a circuit is set forth and given the general reference character 1100.
Circuit 1100 includes transistors (T1102 and T1104) connected in series. Transistor T1102 has a control gate connected to receive input IN1 and transistor T1104 has a control gate connected to receive input IN2. Circuit 1100 may illustrate a common construction of transistors, such as high-voltage breakdown transistors in a semiconductor device, such as a non-volatile semiconductor memory device, as just one example.
Conventional high-voltage breakdown transistor 1000, as illustrated in FIG. 10, cannot be arranged so that two transistors are arranged in series and sharing the same source/drain region. This is due to the gate 112 being disposed over the element region end 122. In order to construct circuit 1100 with two conventional high-voltage breakdown transistors 1000, two separate source/drain regions 116 must be used, one source/drain region for each conventional high-voltage breakdown transistor 1000. The source/drain regions may then be electrically connected with an interconnect layer. Such a configuration takes up much more chip area than a configuration in which two transistors share the same source/drain region
Another drawback to conventional high-voltage breakdown transistor 1000, as illustrated in FIG. 10, is that the gate oxide film may be subjected to etching during the etching of a silicon nitride film. In this case, a gate oxide film having a large thickness (50-100 nm) can be implemented but a small gate oxide thickness (20-30 nm) may be difficult to reliably implement due to film thickness control.
In view of the above discussion, it would be desirable to provide a semiconductor device that may be capable of obtaining a sufficient high breakdown voltage. It would also be desirable to provide the semiconductor device while including semiconductor devices that may not operate at a high voltage. It would also be desirable to provide the semiconductor device included on a semiconductor memory device including non-volatile memory cells.
According to the present embodiments, a semiconductor device including an insulated gate field effect transistor (IGFET) is disclosed. The IGFET may be formed in an element region defined by an element isolation region formed on a semiconductor substrate. A covering portion may cover at least a portion of an end of the element region. A covering portion may be formed essentially of the same material as a side wall of a gate of an IGFET. A source/drain region may be formed using a gate and the covering portion as a mask. In this way, a distance between an intra-substrate high-concentration region and a source/drain region in an end area of the element region may remain sufficient and an IGFET breakdown voltage may be improved.
According to one aspect of the embodiments, a semiconductor device may include an insulated gate field effect transistor (IGFET) formed in an element region defined by an element isolation region. A covering portion may cover at least an end portion of the element region and may be formed from the substantially the same material as a side wall formed on a side surface of a gate of the IGFET
According to another aspect of the embodiments, the covering portion may provide a mask during the formation of a source/drain region of the IGFET.
According to another aspect of the embodiments, the formation of the source/drain region may include the formation of a high impurity concentration region and the formation of a low impurity concentration region and the covering portion may provide a mask during the formation of the high impurity concentration region.
According to another aspect of the embodiments, a second IGFET, which shares the source/drain region, may be formed.
According to another aspect of the embodiments, the covering portion may include a silicon oxide film.
According to another aspect of the embodiments, the covering portion may be formed in a ring along an end of the element region.
According to another aspect of the embodiments, the covering portion may cover at least a portion of the element isolation region.
According to another aspect of the embodiments, a semiconductor device may include a non-volatile memory transistor, a first insulated gate field effect transistor (IGFET), and a high breakdown-voltage IGFET. The high breakdown-voltage IGFET may be formed in an element region defined by an element isolation region. A covering portion may cover at least an end of the element region. The covering portion may be formed from essentially the same material as a side wall formed on a side surface of a gate of at least one of the group including the non-volatile memory transistor, the first IGFET and the high breakdown-voltage IGFET. The covering portion may provide a mask during the formation of a source/drain region of the high breakdown-voltage IGFET.
According to another aspect of the embodiments, the covering portion may include a silicon oxide film.
According to another aspect of the embodiments, the first IGFET may be included in a first circuit coupled to receive a first power supply potential greater than a ground potential. The high breakdown-voltage IGFET may be included in a second circuit coupled to receive a second power supply potential higher than the first power supply potential.
According to another aspect of the embodiments, the second circuit may be coupled to provide a write potential to the non-volatile memory transistor.
According to another aspect of the embodiments, a second high breakdown-voltage IGFET, which shares the source/drain region, may be formed in the well.
According to another aspect of the embodiments, the covering portion may be in the form of a ring along an end of the element region.
According to another aspect of the embodiments, the covering portion may cover at least a portion of the element isolation region.
According to another aspect of the embodiments, a semiconductor device may include a plurality of insulated gate field effect transistors (IGFETs) including a first IGFET. The first IGFET may be formed in an element region defined by an element isolation region formed on a semiconductor substrate. A method for manufacturing the semiconductor device may include the steps of using a first gate of the first IGFET as a mask to form a first source/drain region having a first impurity concentration, forming a first side wall on a side surface of a gate of at least one of the plurality of IGFETs while forming a covering portion that covers at least an end of the element region, and using the gate of the first IGFET, the first side wall and the covering portion as a mask to form a second source/drain region having a second impurity concentration in the first source/drain region. A second impurity concentration may be higher than the first impurity concentration.
According to another aspect of the embodiments, the plurality of IGFETs may include a non-volatile memory transistor and a second IGFET. The second IGFET may be included in a first circuit coupled to receive a first power supply potential. The first power supply potential may be greater than a ground potential. The first IGFET may be included in a second circuit coupled to receive a second power supply potential. The second power supply potential may be greater than the first power supply potential.
According to another aspect of the embodiments, the step of forming the first side wall may include forming the first side wall on the gate of the first IGFET.
According to another aspect of the embodiments, the step of forming the first side wall may include forming the first side wall on the gate of the second IGFET.
According to another aspect of the embodiments, the step of forming the first side wall may include forming the first side wall on the gate of the non-volatile memory transistor.
According to another aspect of the embodiments, the covering portion may include a silicon oxide film.